The clock-path sampling point can be tweaked with respect to datapath sampling point, significantly improving the performance of mixed reach operation from VSR to LR. Sampling point optimization: The digital block can fine-tune performance over a wide range of channels by adjusting the clock sampling.This increases boost for long channels and reduces unwanted boost for short channels, thus implementing true VSR to LR operation. Implementing CTLE and having additional boost amplifier/suppressor circuits extends the dynamic range. Unwanted boost in CTLE, while operating in a low loss channel, is equally as challenging as deficient boost at high loss. Continuous time linear equalization (CTLE) with additional boost amplifier/suppressor: The dynamic range of CTLE boost is an important consideration for operation across the channel loss profile.The PHY starts as a generic LR PHY but self-adapts to the best configuration suitable for a given reach. The current pass results are monitored and used to adjust the adaptation targets of the next pass. Adaptive adaptation: Running the adaptation in multiple passes achieves an optimized configuration.Optimum adaptation for superior performance across VSR to LR with no external intervention These features are adaptive adaptation and temperature tracking, which further optimize performance in real world scenarios. There are more essential features a 112 SerDes IP can offer that go beyond power, performance, and area.
Similarly, digital blocks can help analog blocks compensate for linearity and other analog impairments across process, voltage, and temperature variations. For instance, analog blocks can help digital blocks with signal pre-conditioning which can unburden the digital signal processor (DSP), significantly reducing power and providing robust bit error rate (BER) performance. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compliance is not enough.Ī 112G SerDes PHY architecture with the right mix of analog and digital blocks is the most optimized implementation for best performance, lowest power, and smallest area. Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc.
0 kommentar(er)
